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| LEADER |
00000nam a2200000 4500 |
| 008 |
250305b |||||||| |||| 00| 0 eng d |
| 020 |
|
|
|a 978-93-87523-89-0
|
| 082 |
|
|
|a 681.32
|b Kat
|
| 100 |
|
|
|a Katre, J. S
|
| 245 |
|
|
|a Digital System Design- Semester IV Electronics Engineering
|
| 260 |
|
|
|a Pune
|b Tech-Max
|c 2018
|
| 300 |
|
|
|a Module 6
|
| 650 |
|
|
|a Register Transfer Language
|9 2702
|
| 650 |
|
|
|a Introduction to VHDL
|9 2703
|
| 700 |
|
|
|a Petkar, Sharmila J
|9 2704
|
| 700 |
|
|
|a Joshi, Vaishali S
|9 2635
|
| 952 |
|
|
|0 0
|1 0
|2 ddc
|4 0
|6 681_320000000000000_KAT
|7 0
|9 31453
|a 00000013
|b 00000013
|d 2025-03-05
|l 0
|o 681.32 Kat
|p 300566
|r 2025-03-05 15:50:47
|w 2025-03-05
|y BK
|
| 999 |
|
|
|c 10453
|d 10453
|